Wolmer’s Trust High School for Girls
Upper and Lower Six Teacher: Mrs. McCallum-Rodney
S R LATCH
What is a Latch?
· A latch is a kind of bistable multivibrator, an electronic circuit which has two stable states and thereby can store one bit of information.
· A circuit incorporating latches has state; its output may depend not only on its current input, but also on its previous outputs. Such a circuit is described as sequential logic.
· When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset.
· It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates.
· The stored bit is present on the output marked Q.
· To fully appreciate this latch, you will need to remember the Truth Table for NOR, as shown below:
If you take a close look at the table, you will recognise that, as long as one of the input is on a high (1) the output gives a low(0).
This shows that, as long as a 1 is included in the input the output is 0.
· In addition, it is important to note that when S = 1 and R = 0, this is the set state which should give an output (Q) of 1, and obviously Q’ (representing NOT Q) will be 0.
· To Reset, S = 0 and R = 1, this should give an output of 0 for Q and 1 for Q’.
· To store the latest output in memory, S = 0 and R = 0.
· The input of S = 1 and R = 1, is not used because:
1. The result will be Q= 0 and Q’ = 0. Why? Based on the NOR gate truth table, once a 1 is in the input the result is 0. Since both inputs have 1, the output is definitely a 0 for both outputs. This goes against the complement nature of the outputs.
2. when storage is to take place after this input, depending on the gate that is activated first, the output will be different. Therefore, each gate gives a different storage for Q, depending on which one is activated first. This is unstable and unreliable. Therefore, this input combination is not used.
· Consider the Characteristic Table of the SR Latch using NOR gates
|
Inputs |
Outputs | ||
|
S |
R |
Q |
Q’ |
|
0 |
0 |
Memory | |
|
0 |
1 |
0 |
1 |
|
1 |
0 |
1 |
0 |
|
1 |
1 |
Not used | |
SR Latch using NAND gates
· This is a variety of the simple SR latch built with NAND (Not AND) logic gates.
· Set and reset now become active low signals (0), denoted S and R respectively.
· To fully appreciate this latch, you will need to remember the Truth Table for NAND, as shown below:
If you take a close look at the table, you will recognise that, as long as one of the input is on a low (0) the output gives a high(1).
This shows that, as long as a 0 is included in the input the output is 1.
· To Reset, S = 1 and R = 0, this should give an output of 0 for Q and 1 for Q’.
Please note, that 1 is not the turn on state anymore; 0 is the turn on state
· To store the latest output in memory, S = 1 and R = 1.
· The input of S = 0 and R = 0, is not used because:
1. The result will be Q= 1 and Q’ = 1. Why? Based on the NAND gate truth table, once a 0 is in the input the result is 1. Since both inputs have 0, the output is definitely a 1 for both outputs. This goes against the complement nature of the outputs.
2. when storage is to take place after this input, depending on the gate that is activated first, the output will be different. Therefore, each gate gives a different storage for Q, depending on which one is activated first. This is unstable and unreliable. Therefore, this input combination is not used.
· Consider the Characteristic Table of the SR Latch using NAND gates
|
Inputs |
Outputs | ||
|
S |
R |
Q |
Q’ |
|
0 |
0 |
Not Used | |
|
0 |
1 |
1 |
0 |
|
1 |
0 |
0 |
1 |
|
1 |
1 |
Memory | |
· It brings us to the point that - Set and reset now become active low signals, denoted S and R respectively.
Otherwise, operation is identical to that of the SR latch.
· Historically, SR-latches have been predominant despite the notational inconvenience of active-low inputs; because NAND gates are cheaper to produce than NOR gates.
