Wolmer’s Trust High School for Girls
Upper and Lower Six Teacher: Mrs. McCallum-Rodney
D-Flip Flop
INTRODUCTION
· When using NOR gates for the SR Latch:
o there is no need for S=R=0 (i.e. memory) because if you remove the clock, the memory will stay, and if you put back the clock, the memory changes.
o The input of S=R=1, is not used. There is a way to ensure that input does not go through. Solution? Make S and R complement each other at all times.
· Consider the circuit below:
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· Now we remove the need for two inputs for 1 data.
· Therefore,
o to set the flip flop, S = 1
o to reset the flip flop, S = 0
Why focus on S? Because, R is the complement.
· Data Storage is normally used using D Flip Flop.
· D Flip Flop is a 1-bit storage.
· Bits are stored in a D Flip Flop.
FURTHER EXPLANATION
· An RS-flip flop is rarely used in actual sequential logic.
· However, it is the fundamental building block for the very useful D-flip flop.
· The D-flip flop has only a single data input.
· That data input is connected to the S input of an RS-flip flop, while the inverse of D is connected to the R input.
· To allow the flip flop to be in a holding state, a D-flip flop has a second input called ``Enable'' – which is the clock.
· The Clock-input is AND-ed with the D-input, such that when Clock=0, the R and S inputs of the RS-flip flop are 0 and the state is held.
· When the Clock-input is 1, the S input of the RS flip flop equals the D input and R is the inverse of D.
· Hence, the value of D determines the value of the output Q when Clock is 1.
v At A, clock and data are high. Q goes high and stays high until B.
v At B, clock is high and data is low. Q goes low and stays low until C.
v At C, clock and data are both high. Q goes high and stays high until E.
v Q does not change during clock pulse D, because clock and data are still both high.
v At E, data is low, so Q goes low.
v At F, data is high so Q goes high.
